As integration levels have moved up scale, it has been necessary to decrease channel lengths and thin gate oxide layers for insulated-gate field-effect transistors. The reduction of device dimensions results in a number of short-channel effects which readily manifest themselves in simple devices. One short-channel effect is punchthrough, which results in significant current leakage during transistor "off" states. Effectively, when punchthrough is present, there is no true "off" state. This effect has been mitigated by the use of anti-punchthrough implants in the channel region. For N-channel devices, a low-dosage boron implant is commonly used; for P-channel devices, a low-dosage phosphorus or arsenic implant is used. Another short-channel effect is hot electron injection into the gate oxide layer. This phenomenon results in a reduction of threshold voltage over time. The cause is generally recognized to be a combination of high electric field at the transistor drain and collisions between electrons flowing through the channel with the silicon crystal lattice. Hot electron injection can be reduced by oxidizing the gate edge near the drain. This not only increases gate oxide layer thickness at the gate edge, but also tends to round the gate edge. In addition, lightly-doped drain (LDD) structures have been almost universally adopted for devices at the VLSI level and beyond. An LDD device has a lightly-doped drain region adjacent the channel and a heavily-doped drain region adjacent the lightly-doped drain region, but set back from the channel.
Transistors having LDD structures are generally fabricated using permanent dielectric spacers which are formed on the sidewalls of the device gates. N.sup.- and P.sup.- implants are performed before spacer formation; N.sup.+ and P.sup.+ implants are performed after spacer formation. As spacers are designed to have sufficient height and density to trap ions which are being implanted directly above them, a spacer will result in ions being implanted in a region of the substrate that is offset from the gate edge a distance that is equal to the width of the spacer.
Within the past several years, the fabrication of LDD structures has been described using disposable spacers. By reversing the order of the LDD N.sup.- and P.sup.- implantation steps with respect to the N.sup.+ and P.sup.30 implantation steps, respectively, a reduction in process complexity can be achieved.